FIG. 1 shows a conventional six element flipflop (pushpull) type static memory 100 having an NxM matrix of memory cells such as cell 110:i arranged in N rows 1,2,3 . . . (i-1),i,(i plus 1). . . N and M columns 1,2,3 . . . (i-1),i, (i plus 1) . . . M.
In order to write into memory 100 at cell 110:i, column decoder 112 selects the i-th column via decoder transistors 113(lt):i and 113(rt):i, and applies data-in of the form D (a high voltage) and D(bar) (a low voltage) simultaneously to all of the cells in the i-th column via data lines 114D. As shown in FIG. 1, D is applied to the left side of the i-th column cells through data line 114D(lt), and D(bar) is applied to the right side of the i-th column cells through data line 114D(rt). The i-th row is then selected by row decoder 118 which applies a high access voltage to all of the cells in the i-th row via row lead 120R:i. The write access voltage activates gate 122 of each row access transistor 124(lt) and 124(rt) along the i-th row, exposing cell nodes 128 (lt) and 128(rt) therein to the data lines 114D(lt) and 114D(rt). Only cell 110:i at the intersection of the i-th row and i-th column receives both the write access voltage and the pair of data-in voltages.
Addressed cell 110:i is driven into one of two stable storage states by the D and D(bar) voltages. Either storage transistor 132(rt) conducts and 132(lt) is turned off representing a stored binary "0" (as shown in FIG. 1) or storage transistor 132(rt) is off and 132(lt) is conducting representing a stored binary "1".
After the write cycle, the desired state is maintained in cell 210:i by a trickle standby current (about one microamp) from Vcc through load resistor 136 to ground. High impedance, high density polysilicon load resistors have been employed to reduce the standby current. However, polysilicon resistors exhibit large flucuations in resistance due to manufacturing tolerence requirements, and result in lower yields.
In order to read the data stored at cell 110:i, a high read voltage is applied to both the left and right sides of every cell of memory 100 via sense amplifier 112 and data lines 114D(lt) and 114D(rt). After the data line transients have settled, a high access voltage is applied to gates 122 of each access transistor 124(lt) and 124(rt) of the i-th row. Each cell of the i-th row provides a low impedance path from either the left data line or the right data line to ground through the conducting branch of the cell. Read current 140 through each low impedance path causes the read voltage on that side of the cell to drop. The read voltage on the non-conducting side of each cell remains high.
The voltage difference between the data leads 114D(lt) and 114D(rt) of selected column "i" is sensed by sense amplifier 112. The binary "0" stored in cell 110:i causes a low read voltage on data line 114D(rt) (due to the read current 140:i flowing from data line 114(rt) through access transistor 132(rt) to ground. Sense amplifier 142 responds to the left-high, right-low status of the i-th column by processing a "0" out of memory 100.
The read current through each cell on the accessed row, whether monitored or unmonitored, is about 100 microamps. The total read current in a 16K embodiment of memory 100 (128 rows by 128 columns) is therefore about 12.8 milliamps, which presents heating problems and related cell density limitations.
In addition to excessive read currents, conventional static memory 100 of FIG. 1 also has a high read capacitance which must be charged by the read voltage on data lines 114D prior to the application of the access voltage on row lead 120R:i. The primary element of the read capacitance is between data lines 114D and ground (Cap-D), which consumes about 30% of the read cycle time for precharging. If cell 110:i is row accessed before the data line transients have settled, sense amplifier 142 may compare the two initial transient voltages on data lines 114D(lt) and 114D(rt) and process erroneous data. Static prior art memories rely on the steady state voltage difference between the left and right lines, and can not be prematurely accessed during the transient period associated with Cap-D.
Memory cells 110 must be highly stable for preventing write disturb (the arbitary flipping of the bistable addressed cell or partially addressed cells in the addressed row by the access voltages). The cells therefore require the application of both D and D(bar) voltages in order to change storage states. Cell stability is also relied on to prevent read disturb (the arbitary flipping due to the high read voltage). During both write and read, each cell 110 along the i-th row is fully accessed by the high voltage on row lead 120R:i, and easily susceptible to flipping.
Two conventional techniques are employed to prevent write and read disturb. First the cells 110 are designed as stable as possible, ie. the cells have large storage transistors 132 in a low density matrix. Second, the voltage applied to all of the remaining columns (nonaccessed columns) is maintained absolutely constant. The prevention of write and read disturb places severe restraints on the design of prior art memories resulting in a loss of density and access speed.
In general the prior art static RAMs have low density and performance due to write and read disturb considerations. The prior art cells are not uniquely accessed. They are accessed by the row, which creates a susceptibility toward write and read disturb.